(China (Mainland))
Product Summary
The CY7C1380D-167AXC is a 18-Mbit Pipelined SRAM. It integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The CY7C1380D-167AXC inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3 [2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.
Parametrics
CY7C1380D-167AXC absolute maximum ratings: (1)Storage Temperature: –65℃ to +150℃; (2)Ambient Temperature with Power Applied: –55℃ to +125℃; (3)Supply Voltage on VDD Relative to GND: –0.3V to +4.6V; (4)DC Voltage Applied to Outputs in Tri-State: –0.5V to VDDQ + 0.5V; (5)DC Input Voltage: –0.5V to VDD + 0.5V.
Features
CY7C1380D-167AXC features: (1)Supports bus operation up to 250 MHz; (2)Available speed grades are 250, 200 and 167 MHz; (3)Registered inputs and outputs for pipelined operation; (4)3.3V core power supply; (5)2.5V / 3.3V I/O operation; (6)Fast clock-to-output times; (7)Provide high-performance 3-1-1-1 access rate; (8)User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences; (9)Separate processor and controller address strobes; (10)Synchronous self-timed writes; (11)Asynchronous output enable; (12)Single Cycle Chip Deselect; (13)Offered in JEDEC-standard lead-free 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages.
Diagrams
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 CY7C1380D-167AXC |
Cypress Semiconductor |
SRAM 512Kx36 3.3V COM 1CD Sync PL SRAM |
Data Sheet |
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CY7C1380D-167AXCT |
Cypress Semiconductor |
SRAM 512Kx36 3.3V COM 1CD Sync PL SRAM |
Data Sheet |
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